Delay between Clk active and Rst High set to 45,000 clock cycles
Automatic min/max measurement at Atr, Card or Reader step

TermSim assumes parity error with a small error signal window
TermSim sends parity errors and repeat the disputed character with a 12.8 etus delay

TermSim send a PPS Request with PPS1 = '96'
TermSim sends a first block with a parity error, then sends the second one with a parity + LRD error

TermSim sends a header 5etus after the clock is resumed
TermSim sends data with an opposite delay set to 12etus - 1etu = 12.8 µs

The Card setting leads to an automatic test chaining, using user-defined Voltage, PPS1 and frequencies
Schmoo-plot Frequency vs Vcc

ICC measurement at ATR step